This is probably my favorite go-to-component next to the resistor arrays. I can use 3 wires from the device and control 8 x n outputs. n = the number of SN74HC595 in series. I have done logic tables for Least Significant Bit First and Most Significant Bit First.
What is a shift register?
a register that is designed to allow the bits of its contents to be moved to left or right.
A shift register is a type of digital circuit using a cascade of flip flops where the output of one flip-flop is connected to the input of the next. They share a single clock signal, which causes the data stored in the system to shift from one location to the next. By connecting the last flip-flop back to the first, the data can cycle within the shifters for extended periods, and in this form they were used as a form of computer memory. In this role they are very similar to the earlier delay line memory systems and were widely used in the late 1960s and early 1970s to replace that form of memory.
SISO: Serial In, Serial Out, Destructive
These are the simplest kind of shift registers. The data string is presented at “Data In”, and is shifted right one stage each time “Data Advance” is brought high. At each advance, the bit on the far left (i.e. “Data In”) is shifted into the first flip-flop‘s output. The bit on the far right (i.e. “Data Out”) is shifted out and lost.
The data is stored after each flip-flop on the “Q” output, so there are four storage “slots” available in this arrangement, hence it is a 4-bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As “Data In” presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at “Data Advance” each time—this is called clocking or strobing) to the register, this is the result. The right hand column corresponds to the right-most flip-flop’s output pin, and so on.
So the serial output of the entire register is 00010110. It can be seen that if data were to be continued to input, it would get exactly what was put in (10110000), but offset by four “Data Advance” cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.
This arrangement performs destructive readout – each datum is lost once it has been shifted out of the right-most bit.
SIPO: Serial-in parallel-out
This configuration allows conversion from serial to parallel format. Data input is serial, as described in the SISO section above. Once the data has been clocked in, it may be either read off at each output simultaneously, or it can be shifted out.
In this configuration, each flip-flop is edge triggered. All flip-flops operate at the given clock frequency. Each input bit makes its way down to the Nth output after N clock cycles, leading to parallel output.
In cases where the parallel outputs should not change during the serial loading process, it is desirable to use a latched or buffered output. In a latched shift register (such as the 74595) the serial data is first loaded into an internal buffer register, then upon receipt of a load signal the state of the buffer register is copied into a set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.
PISO: Parallel In, Serial Out
This configuration has the data input on lines D1 through D4 in parallel format, D1 being the most significant bit. To write the data to the register, the Write/Shift control line must be held LOW. To shift the data, the W/S control line is brought HIGH and the registers are clocked. The arrangement now acts as a PISO shift register, with D1 as the Data Input. However, as long as the number of clock cycles is not more than the length of the data-string, the Data Output, Q, will be the parallel data read off in order.